Conventionally, a phase-locked loop circuit (hereinafter referred to as a PLL circuit) has been known as a circuit which generates clocks with an arbitrary synchronous frequency with input signals.
A PLL circuit is mounted with a variable frequency oscillator, and compares a phase of an input signal with that of a feedback signal output from the oscillator. The PLL circuit performs negative feedback control so that the input signal is synchronized with the feedback signal (i.e., to maintain a fixed phase relationship between the input signal and the feedback signal). This control operation is called locking (also called phase locking). In addition, the time required for such control operation is called lock time (also called phase-lock time).
Lock time is generally determined by the time constant of a loop filter in a PLL circuit. If the time constant is large (if the cutoff frequency is low), locking is performed slowly, whereas if the time constant is small (if the cutoff frequency is high), locking is performed quickly. If the lock time is short, the control operation can be performed in a short time after a signal input; however, since the operation is adversely affected in the case where the input signal has noise, it is difficult to maintain stable control operation. Notwithstanding the aforementioned circumstance, a PLL circuit which can reduce the lock time independently of the operating conditions of a circuit and the manufacturing conditions is known (see Patent Document 1, for example).
[Patent Document 1] Japanese Patent Laid-Open No. 2001-251186 (page 5, FIG. 1)
However, in order to reduce the lock time, a voltage-controlled oscillator (hereinafter also referred to as a VCO) is required to operate with a stable oscillation frequency even when there is no signal input (hereinafter, this operation is referred to as a free-running oscillation) at the time when the PLL circuit starts its operation. In order to create desirable conditions for a stable free-running oscillation, a switch circuit has to be provided between an output of a loop filter (hereinafter also referred to as an LF) and an input of the VOC. A signal output from the LF corresponds to a signal obtained by removing unnecessary high frequency components from an output signal of the phase detector (a signal which represents the difference in phase between two signal inputs). The analog voltage value of this signal controls the frequency of a signal output to the VCO. Therefore, when a switch circuit is provided, an input signal of the VCO becomes unstable when it is mixed with noise or the like, and this will be a factor which makes the operation of the PLL circuit unstable. As a result, it is necessary to wait until the conditions for a stable free-running oscillation are obtained, and in such a case, it makes no sense to provide a switch circuit in order to reduce the lock time.